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Design Assessment Report

Early Analysis & Risk Prediction

The Design Assessment's primary goal is to make and report an assessment of the success/failure potential of Placement and Routing of an FPGA design, as well as the potential of meeting timing or not.

Its objectives are:

  • Provide users with an early heads-up (post-synthesis and optimization) on the potential impediments to the placement or routing of the FPGA design. This will enable users to adjust the settings, the constraints, or even the RTL.
  • Speed up debug and optimization time as well as save compute resources for FPGA designs, especially those that have low potential to successfully place or route.
  • Give end-users actionable steps to mitigate the challenges. For instance,
    • review stringent timing constraints,
    • review the flow settings (synthesis, optimization, placement and routing), or
    • adjust Floorplanning constraints to reduce congestion or unbalanced assignment of logic blocks to certain areas of the target device.
  • Highlight the root causes of placement, routing or timing failures due to factors like
    • high utilization of specific resources,
    • high intrinsic congestion, artificial congestion due to user constraints, or
    • other insights related to the FPGA design’s profile.
  • In some cases, the proposed user actions recommend the use of particular recipes in the Plunify toolset.

How to use

  1. Synthesize, Place or Route the FPGA design. The Design Assessment Report provides insights at different stages of compilation.
  2. Firstly, analyse the design netlist by executing the following command in the InTime Tcl Console: 
    plunify> results extract root
    This may take a while.
  3. Next, generate the assessment report by entering 
    plunify> results assess_design

Output report

  1. For the original project ("Root parent"), the report will be generated as <project>/plunify.jobs/root/<project name>_design_assessment.rpt
  2. For InTime strategies, the report will be generated as <project>/plunify.jobs/<job ID>/<strategy name>_design_assessment.rpt

Sample Report

The report begins with an overview of the design / project, FPGA tool version and the compilation stage that is analysed;

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--------------------------------------------------------------------------------------------
| Design Assessment Report - <Design / Project file>                                       | 
--------------------------------------------------------------------------------------------
|                                                                                          | 
| InTime v3.3.2 (Build e26de52)                                                            | 
|                                                                                          | 
| Generated on: Fri Mar 29 17:17:51 2022. Time taken: 00:00:06.025                         | 
| Toolchain: <FPGA tool version>                                                           | 
| Device: <Target device part>                                                             | 
| Current Project: <Full path to the design / project file>                                | 
| Top level: <Toplevel module name>                                                        | 
| Stage: <Compilation stage: Post-Synthesis / Placement / Route>                           |
... and the types of metrics used to evaluate the design. 

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|                                                                                          | 
| Contents:                                                                                | 
| 1. (Post-Route) Logic Utilization Analysis                                               | 
| 2. (Post-Route) Routing Node Overlaps                                                    | 
| 3. (Post-Route) BRAM / DSP utilization across dies                                       | 
| 4. (Post-Route) CLB distribution across dies                                             | 
| 5. (Post-Route) Congestion induced by User Physical Constraints (PBlocks)                | 
| 6. (Post-Route) General Design Attribute Checks                                          | 
|                                                                                          | 
--------------------------------------------------------------------------------------------

The first table contains a quick synopsis of the potential of failure to give the reader an immediate "design score". 

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------------------------------------------
| Executive Summary         | Risk Level | 
------------------------------------------
| Risk of Placement Failure | Medium     | 
| Risk of Routing Failure   | High       | 
| Risk of Timing Violations | High       | 
------------------------------------------

Subsequent sections present the details, and is usually in the format:

  • Data;
  • Observations and summarized interpretation of the data; and finally,
  • Suggested next steps
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1.1 (Post-Route) Logic Utilization Analysis
===========================
Checks the potential impact of different LUT primitives on design congestion, placement, routing and timing.
-----------------------------------------
| ID    | Description | Usage   | %     | 
-----------------------------------------
| 1.0.1 | Total LUTs  | 2004097 | 70.32 | 
| 1.0.2 | LUT1        | 28863   | 1.44  | 
| 1.0.3 | LUT2        | 239923  | 11.97 | 
| 1.0.4 | LUT3        | 357927  | 17.86 | 
| 1.0.5 | LUT4        | 357902  | 17.86 | 
| 1.0.6 | LUT5        | 319037  | 15.92 | 
| 1.0.7 | LUT6        | 700445  | 34.95 | 
-----------------------------------------

The total LUT utilization of 70.32% is high and may lead to difficulty of placement.

LUT1% + LUT2% + LUT3% = 31.27% indicates either poor Synthesis/Mapping of RTL coding styles that favor low-input LUT mapping.

LUT5% + LUT6% = 50.87% indicates a possibility of local congestion in certain blocks of the design and may lead to routing failures.

Summary:
    1. Logic (LUT) utlization analysis shows areas of concern for the success of the placement (high Total LUT utilization).
    2. Sub-optimal Synthesis/Mapping or RTL Coding Style leading to high utilization of LUT1, LUT2 and LUT3.

Proposed User Actions:
    1. Please review Synthesis/Mapping to reduce Total LUT usage.
    2. Run InTime Quick Assessment Recipe.

Using the Report

It is recommended that the reader checks each metric and its suggested action(s), to explore how to resolve the highlighted issues.